Indian Economy News

Government of India creating enabling environment for Semiconductor Design Community with direct access to National Chip Design Infrastructure

The ChipIN Centre, one of the largest facilities at C-DAC, aims to strengthen India’s semiconductor ecosystem by providing access to advanced electronic design automation (EDA) tools and solutions. Catering to academic institutions and entrepreneurs, the centre offers state-of-the-art tools for semiconductor design workflows, supporting the entire chip design cycle up to 5 nm nodes. The centre also provides compute and hardware infrastructure, IP cores, and expertise for chip design, fabrication at the SCL foundry, and packaging under the Chips to Start-up (C2S) Programme and Design Linked Incentive (DLI) Scheme of the Ministry of Electronics and Information Technology (MeitY). Currently, the ChipIN Centre serves over 20,000 students across 250+ academic institutions and 45 start-up projects. The goal is to reach 85,000 students within the next five years, empowering them to design semiconductor chips and contribute to India’s Atmanirbhar Bharat (self-reliant India) vision.

In response to growing demand, Siemens has expanded the usage of its EDA tools from 120 to 250+ colleges under the C2S Programme, also extending its Veloce™ hardware-assisted verification solution to DLI-approved companies. The Veloce platform, which includes Veloce Strato hardware, Veloce Apps, and Veloce Protocol Solutions, provides the necessary compute capacity for complex System-on-chip (SoC) and integrated circuit (IC) designs, with a facility of 128 CPU cores and 640 million gates. This collaboration is crucial in advancing India's semiconductor capabilities and empowering the next generation of engineers, researchers, and entrepreneurs. Siemens’ contribution aligns with India’s commitment to building a self-sustaining semiconductor ecosystem, driving technological innovation, and positioning the country as a global leader in the semiconductor sector.

Disclaimer: This information has been collected through secondary research and IBEF is not responsible for any errors in the same.